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LTC3866 1 3866fb typical application features description current mode synchronous controller for sub milliohm dcr sensing the lt c ? 3866 is a single phase current mode synchronous step - down switching regulator controller that drives all n-channel power mosfet switches. it employs a unique architecture which enhances the signal - to - noise ratio of the current sense signal , allowing the use of a very low dc resistance power inductor to maximize the efficiency in high current applications. this feature also reduces the switching jitter commonly found in low dcr applications. the LTC3866 also includes a high speed remote sense dif- ferential amplifier, a programmable current sense limit that can be selected to 10 mv , 15 mv , 20 mv , 25 mv or 30 mv, and dcr temperature compensation to limit the maximum output current precisely over temperature. the LTC3866 also features a precise 0.6v reference with a guaranteed limit of 0.5% that provides an accurate output voltage from 0.6v to 3.5v. a 4.5v to 38v input voltage range allows it to support a wide variety of bus voltages and various types of batteries. the LTC3866 is offered in a low profile 24-lead 4mm 4mm qfn and 24-lead exposed pad fe packages. applications n sub milliohm dcr current sensing n high efficiency: up to 95% n selectable current sensing limit n programmable dcr temperature compensation n die overtemperature thermal shutdown n 0.5% 0.6 v output voltage accuracy n programmable fixed frequency 250khz to 770khz n high speed differential remote sense amplifier n wide input voltage range: 4.5v to 38v n output voltage range: 0.6v to 3.5v with diffamp n adjustable soft-start or output voltage tracking n foldback output current limit n short- circuit soft recovery n output overvoltage protection n 24- lead (4mm 4mm) qfn and 24-lead fe packages n computer systems n telecom systems n industrial and medical instruments n dc power distribution systems l, lt , lt c , lt m , burst mode, opti-loop, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending. high efficiency, 1.5v/30a step-down converter with very low dcr sensing freq mode/pllin run pgood tk/ss itemp ith extv cc v fb v in diffout intv cc diffp boost diffn tg snsd + sw sns ? bg c out 470f 2 0.1f r2 931 r1 4.64k 3866 ta01a 30.1k 100k 0.1f 20k 10k v out 1.5v 30a 4.7f c1 220nf c2 220nf 1.5nf 220pf 220f v in 4.5v to 20v 0.33h dcr = 0.32m snsa + pgnd ilim clkout LTC3866 sgnd efficiency vs load current and mode load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3866 ta01b 0 0.1 ccm pulse skipping burst mode operation v in = 12v v out = 1.5v l = 0.33h (dcr = 0.32m typ)
LTC3866 2 3866fb absolute maximum ratings input supply voltage .................................. C0.3 v to 40 v topside driver voltage ( boost ) ................ C0.3 v to 46 v switch voltage ( sw ) ..................................... C5 v to 40 v intv cc , extv cc , run , pgood , boost - sw voltages .................................... C0.3 v to 6 v snsd + , snsa + , sns C voltages ............. C0.3 v to intv cc mode / pllin , ilim , tk / ss , freq , diffout voltages ................................. C0.3 v to intv cc (note 1) order information lead free finish tape and reel part marking* package description temperature range LTC3866efe#pbf LTC3866efe#trpbf LTC3866fe 24-lead plastic tssop C40c to 125c LTC3866ife#pbf LTC3866ife#trpbf LTC3866fe 24-lead plastic tssop C40c to 125c LTC3866euf#pbf LTC3866euf#trpbf 3866 24-lead (4mm 4mm) plastic qfn C40c to 125c LTC3866iuf#pbf LTC3866iuf#trpbf 3866 24-lead (4mm 4mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ diffp , diffn ......................................... C0.3 v to intv cc itemp , ith , v fb voltages .................... C0.3 v to intv cc intv cc peak output current .............................. 100 ma operating junction temperature range ( notes 2, 4) ............................................ C40 c to 125 c storage temperature range .................. C65 c to 125 c lead temperature ( soldering , 10 sec ) fe package ....................................................... 300 c 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 freq run tk/ss ith v fb diffout diffn diffp snsd + sns ? snsa + ilim mode/pllin pgood itemp extv cc v in intv cc boost tg sw bg pgnd clkout 25 sgnd ja = 33c/w, jc = 10c/w exposed pad (pin 25) is sgnd, must be soldered to pcb 24 23 22 21 20 19 7 8 9 top view 25 sgnd uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ith v fb diffout diffn diffp snsd + extv cc v in intv cc boost tg sw tk/ss run freq mode/pllin pgood itemp sns ? snsa + ilim clkout pgnd bg ja = 47c/w, jc = 4.5c/w exposed pad (pin 25) is sgnd, must be soldered to pcb pin configuration
LTC3866 3 3866fb electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units main control loops v in input voltage range 4.5 38 v v out output voltage range with diffamp in loop 0.6 3.5 v v fb regulated feedback voltage current ith voltage = 1.2v (note 5) C40 c to 85c C40 c to 125c l l 0.597 0.5955 0.6 0.6 0.603 0.6045 v v i fb feedback current (note 5) C15 C50 na v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 5) 0.002 0.02 % v loadreg output voltage load regulation (note 5) measured in servo loop; ?ith voltage = 1.2v to 0.7v measured in servo loop; ?ith voltage = 1.2v to 1.6v l l 0.01 0.01 0.1 0.1 % % g m error amplifier (ea) transconductance ith =1.2v, sink/ source 5a (note 5) 2 mmho i q input dc supply current normal mode shutdown (note 6) v in = 15v v in = 15v, v run = 0v 3.2 30 50 ma a uvlo undervoltage lockout v intvcc ramping down 3.4 3.75 4.1 v uvlo hys uvlo hysteresis voltage 0.5 v v fbovl feedback overvoltage lockout measured at v fb l 0.64 0.66 0.68 v i snsd + snsd + pin bias current v snsd + = 3.3v l 30 100 na i snsa + snsa + pin bias current v snsa + = 3.3v l 1 2 a a vt_sns total sense signal gain to current comparator (v snsd + + v snsa +)/v snsd + 5 v/v v sense(max) maximum current sense threshold C40c to 85c v sns C = 1.8v, ilim = 0v ilim = 1/4 v intvcc ilim = 1/2 v intvcc or float ilim = 3/4 v intvcc ilim = v intvcc C40c to 125c v sns C = 1.8v, ilim = 0v ilim = 1/4v intvcc ilim = 1/2v intvcc or float ilim = 3/4v intvcc ilim = v intvcc l l l l l l l l l l 9.2 14.2 19.2 23.5 28.5 9 14 19 23.5 28.5 10 15 20 25 30 10 15 20 25 30 10.8 15.8 20.8 26.5 31.5 11 16 21 26.5 31.5 mv mv mv mv mv mv mv mv mv mv i temp dcr temperature compensation current v itemp = 0.3v l 9 10 11 a i tk/ss soft- start charge current v tk/ss = 0v l 1.0 1.25 1.5 a v run run pin on threshold voltage v run rising l 1.1 1.22 1.35 v v run(hys) run pin on hysteresis voltage 80 mv tg t r t f top gate (tg) transition time rise time fall time (note 7) c load = 3300pf c load = 3300pf 25 25 ns ns bg t r t f bottom gate (bg) transition time rise time fall time (note 7) c load = 3300pf c load = 3300pf 25 25 ns ns
LTC3866 4 3866fb electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units tg/bg t d top gate off to bottom gate on delay, synchronous switch-on delay time c load = 3300pf 30 ns bg/tg t d bottom gate off to top gate on delay, top switch-on delay time c load = 3300pf 30 ns t on(min) minimum on- time (note 8) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 5.25 5.5 5.75 v load regulation i intvcc = 0ma to 20ma 0.5 2 % v extvcc external v cc switchover voltage extv cc ramping positive 4.5 4.7 v extv cc voltage drop i extvcc = 20ma, v extvcc = 5v 50 100 mv extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0.4v 225 250 275 khz f high highest frequency v freq > 2.4v 700 770 850 khz r mode/pllin mode/pllin input resistance 250 k i freq frequency setting current 9 10 11 a clkout phase relative to the oscillator clock 180 deg clkout hi clock output high voltage v intvcc = 5.5v 4.5 5.5 v clkout lo clock output low voltage 0 0.2 v pgood output v pgdlo pgood voltage low i pgood = 2ma 0.1 0.3 v i pgd pgood leakage current v pgood = 5.5v 2 a v pgd pgood trip v fb with respect to set output voltage v fb going negative v fb going positive C10 10 % % differential amplifier a v gain C40c to 85c C40c to 125c l l 0.999 0.998 1 1 1.001 1.002 v/v v/v r in input resistance measured at diffp input 80 k v os input offset voltage v diffp = 1.5v, v diffout = 100a 2 mv psrr power supply rejection ratio 5v < v in < 38v 90 db i out maximum sourcing output current 1.5 3 ma v out maximum output voltage v intvcc = 5.5v, i diffout = 300a v intvcc C 1.4 v intvcc C 1.1 v gbw gain-bandwidth product (note 9) 3 mhz sr slew rate (note 9) 2 v/s
LTC3866 5 3866fb electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise specified. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3866 is tested under pulsed load conditions such that t j t a . the LTC3866e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3866i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. note 3: the junction temperature, t j , is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: LTC3866fe: t j = t a + (p d ? 33c/w) LTC3866uf: t j = t a + (p d ? 47c/w) symbol parameter conditions min typ max units on-chip driver tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 bg r down bg pull-down r ds(on) bg low 1.1 note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: the LTC3866 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . note 6: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 7: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 8: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 40% of i max (see minimum on- time considerations in the applications information section). note 9: guaranteed by design. typical performance characteristics efficiency vs load current and mode efficiency vs load current and mode efficiency and power loss vs load current t a = 25c, unless otherwise noted. load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3866 g01 0 0.1 ccm pulse skipping burst mode operation v in = 4.5v v out = 1.5v l = 0.33h (dcr = 0.32m typ) front page circuit load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3866 g02 0 0.1 ccm pulse skipping burst mode operation v in = 12v v out = 1.5v l = 0.33h (dcr = 0.32m typ) front page circuit load current (a) 0 efficiency (%) power loss (w) 89 92 95 94 93 90 91 87 88 84 85 81 82 15 25 3530 3866 g03 86 83 80 15 10 5 0 5 10 20 efficiency power loss v in = 20v v out = 1.5v front page circuit
LTC3866 6 3866fb intv cc line regulation current sense threshold vs ith voltage maximum current sense threshold vs common mode voltage load step (burst mode ? operation) inductor current at light load load step (continuous conduction mode) prebiased output at 1.2v load step (pulse-skipping mode) tracking up and down with tk / ss external ramp typical performance characteristics i load 10a/div 1.5a to 15a v out 100mv/div ac-coupled 20s/div 3866 g04 v in = 12v v out = 1.5v front page circuit i l 10a/div 0a 0a i load 10a/div 1.5a to 15a v out 100mv/div ac-coupled 20s/div 3866 g05 v in = 12v v out = 1.5v front page circuit i l 10a/div 0a 0a i load 10a/div 1.5a to 15a v out 100mv/div ac-coupled 20s/div 3866 g06 v in = 12v v out = 1.5v front page circuit i l 10a/div 0a 0a continuous conduction mode 5a/div pulse-skipping mode 5a/div 10s/div 3866 g07 v in = 12v v out = 1.5v i load = 300ma burst mode operation 5a/div 0a 0a 0a v out 500mv/div v fb 500mv/div 500s/div 3866 g08 v in = 12v v out = 1.5v 0v 0v track/ss 500mv/div v tk/ss 0.2v/div v out 0.5v/div 2.5ms/div 3866 g09 v in = 12v v out = 1.5v 1 load 0v v tk/ss v out input voltage (v) 0 0 intv cc voltage (v) 1 2 3 4 10 20 30 40 3866 g10 5 6 5 15 25 35 v ith (v) 0 ?10 current sense threshold (mv) ?5 5 10 15 40 25 0.5 1.0 1.25 3866 g11 0 30 35 20 0.25 0.75 1.5 1.75 2.0 i lim = 0v i lim = 1/4 intv cc i lim = 1/2 intv cc i lim = 3/4 intv cc i lim = intv cc v sense common mode voltage (v) 0 current sense threshold (mv) 20 30 4.0 3866 g12 10 0 1.0 2.0 3.0 0.5 1.5 2.5 3.5 40 15 25 5 35 i lim = intv cc i lim = 0v i lim = 3/4 intv cc i lim = 1/4 intv cc i lim = 1/2 intv cc t a = 25c, unless otherwise noted.
LTC3866 7 3866fb typical performance characteristics shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature undervoltage lockout threshold ( intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs input voltage tk/ss pull-up current vs temperature maximum current sense threshold voltage vs feedback voltage (current foldback) t a = 25c, unless otherwise noted. feedback voltage (v) 0 maximum current sense threshold (mv) 15 20 25 0.3 0.5 3866 g14 10 5 0 0.1 0.2 0.4 30 35 40 0.6 i lim = intv cc i lim = 3/4 intv cc i lim = 1/2 intv cc i lim = 1/4 intv cc i lim = 0v temperature (c) ?50 tk/ss (a) 1.0 1.2 1.4 150 3866 g15 0.8 0.6 0 0 50 100 ?25 25 75 125 0.2 0.4 1.8 1.6 temperature (c) ?50 run threshold (v) 1.20 1.30 150 3866 g16 1.10 1.00 0 50 100 ?25 25 75 on off 125 1.40 1.15 1.25 1.05 1.35 temperature (c) ?50 598.5 regulated feedback voltage (mv) 599.0 599.5 600.0 600.5 0 50 100 150 3866 g17 601.0 601.5 ?25 25 75 125 temperature (c) ?50 frequency (khz) 500 550 150 3866 g18 450 400 0 50 100 ?25 25 75 125 600 475 525 425 575 v freq = 1.2v input voltage (v) 0 frequency (khz) 500 600 700 40 3866 g19 400 300 0 10 20 30 5 15 25 35 200 100 900 800 v freq = 2.5v v freq = 1.2v v freq = 0v temperature (c) ?50 2.5 uvlo threshold (v) 2.7 3.1 3.3 3.5 4.5 3.9 0 50 3866 g20 2.9 4.1 4.3 3.7 100 ?25 25 75 125 150 rise fall input voltage (v) 0 0 shutdown current (a) 10 30 40 50 100 70 10 20 25 3866 g21 20 80 90 60 5 15 30 35 40
LTC3866 8 3866fb pin functions shutdown current vs temperature (fe/uf) input quiescent current vs input voltage without extv cc quiescent current vs temperature without extv cc freq (pin 1/pin 22): oscillator frequency control input. a 10a current source flows out of this pin. connecting a resistor between this pin and ground sets a dc voltage which in turn programs the oscillator frequency. alterna- tively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. run (pin 2/pin 23): run control input. a voltage above 1.22v turns on the ic. pulling this pin below 1.14v causes the ic to shut down. there is a 1a pull-up current for the pin. once the run pin rises above 1.22v, an additional 4.5a pull-up current is added to the pin. tk/ss (pin 3/pin 24): output voltage tracking and soft- start input. an internal soft- start current of 1.25a charges the external soft-start capacitor connected to this pin. ith (pin 4/pin 1): current control threshold and error amplifier compensation pin. the current comparator trip- ping threshold is proportional with this voltage. v fb (pin 5/pin 2): error amplifier feedback input. this pin receives the remotely sensed feedback voltage to set the output voltage through an external resistive divider connected to the diffout pin or the output. diffout (pin 6/pin 3): output of remote sensing differ - ential amplifier. connect this pin to v fb through a resistive divider to set the desired output voltage. diffn (pin 7/pin 4): negative input of remote sensing differential amplifier. connect this pin close to the ground of the output load. diffp (pin 8/pin 5): positive input of remote sensing differential amplifier. connect this pin close to the output load. snsd + (pin 9/ pin 6): first positive current sense input. this pin is connected to sense the signal of the output inductors dcr, it is to be used with a filter that matches the bandwidth, l/dcr, of the inductor. sns C (pin 10/pin 7): negative current sense input. this negative input of the current comparator is to be connected to the output. snsa + (pin 11/pin 8): second positive current sense input. this input is to be connected to sense the signal of the outputs inductor dcr with a filter bandwidth of five times larger than l/dcr. ilim (pin 12/pin 9): current comparator sense voltage limit. apply a dc voltage to set the maximum current sense threshold for the current comparator. clkout (pin 13/pin 10): clock output pin. the clkout signal is 180 out of phase to the rising edge of the ic internal clock. typical performance characteristics t a = 25c, unless otherwise noted. temperature (c) ?50 shutdown current (a) 30 40 150 3866 g22 20 10 0 50 100 ?25 25 75 125 50 25 35 15 45 input voltage (v) 5 quiescent current (ma) 3.50 3.75 4.00 20 30 3866 g23 3.25 3.00 10 15 25 35 40 2.75 2.50 temperature (c) ?50 quiescent current (ma) 3.2 3.6 150 3866 g24 2.8 2.4 0 50 100 ?25 25 75 125 4.0 3.0 3.4 2.6 3.8
LTC3866 9 3866fb pin functions (fe/uf) pgnd (pin 14/pin 11): power ground. connect to the source of the bottom n-channel mosfet and the negative terminals of the v in and intv cc decoupling capacitors close to this pin. bg (pin 15/pin 12): bottom gate driver output. this pin drives the gate of the bottom n-channel mosfet and swings between intv cc or extv cc and pgnd. sw (pin 16/pin 13): switch node connection. connect this pin to the output filter inductor, bottom n-channel mosfet drain and top n - channel mosfet source . voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . tg (pin 17/pin 14): top gate driver output. this is a float- ing driver to be connected to the gate of the top n - channel mosfet. the voltage swing of this pin equals to intv cc superimposed over the switch node (sw) voltage. boost (pin 18/pin 15): boosted top gate driver supply. the (+) terminal of the booststrap capacitor connects to this pin. this pins swings from a diode voltage drop below intv cc up to v in + intv cc . intv cc (pin 19/pin 16): internal 5.5v regulator output. the internal control circuits are powered from this voltage. decouple this pin to pgnd with a 4.7f low esr tantalum or ceramic capacitor. v in (pin 20/pin 17): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). for applications where the main input power is 5v, tie the v in and intv cc pins together. extv cc (pin 21/ pin 18): external supply voltage input. whenever an external voltage supply greater than 4.7v is connected to this pin, an internal switch will close and bypass the internal low dropout regulator, and the external supply will power the ic. do not exceed 6v on this pin and ensure v in > v extvcc at all times. itemp (pin 22/pin 19): temperature dcr compensation input. connect to a ntc (negative tempco) resistor placed near the output inductor to compensate for its dcr change over temperature. floating this pin or tying it to intv cc disables the dcr temperature compensation function. pgood (pin 23/pin 20): power good indicator output. open-drain logic out that is pulled to ground when the output exceeds the 10% regulation window, after the internal 20s power bad mask timer expires. mode/pllin (pin24/pin 21): mode operation or external clock synchronization. connect this pin to sgnd to set the continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock signal applied to the pin will force the controller into continuous mode of operation and synchronizes the internal oscillator . sgnd (exposed pad pin 25/ exposed pad pin 25): sig- nal ground. this is the ground of the controller. connect compensation components and output setting resistors to this ground. the exposed pad must be soldered to the pcb ground plane.
LTC3866 10 3866fb functional block diagram ? + ? ++ sleep intv cc 0.55v ? + ? + 0.5v ss ? + 1.22v run 1.25a v in ea ith r c c c1 c ss run tk/ss 0.6v ref s r q 5.5v reg active clamp osc mode/sync detect slope compensation uvlo 1 r i thb 1a/5.5a freq clkout mode/pllin itemp 0.6v burst en extv cc ilim ? + ? + i comp i rev f ? + 4.7v f ? + ? + ov uv ? + diffamp ? + amp 0.54v r2 r1 v fb pgood pgnd c vcc c b m1 m2 v out v in c out d b bg sns ? snsa + sw tg boost intv cc diffn diffp snsd + 3866 bd sgnd 0.66v 40k 40k 40k 40k switch logic and antishoot- through ov run on fcnt pll-sync tempsns + c in + v in diffout v out
LTC3866 11 3866fb operation main control loop the LTC3866 uses lt c proprietary current sensing , current mode step- down architecture . during normal operation, the top mosfet is turned on every cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the remote sense amplifier (diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re - references it to the local ic ground reference . the v fb pin receives this feedback signal and compares it to the internal 0.6v reference. when the load current increases, it causes a slight decrease in the v fb pin voltage relative to the 0.6v reference, which in turn causes the ith voltage to increase until the inductors average current equals the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, i rev , or the beginning of the next cycle. the main control loop is shut down by pulling the run pin low. releasing run allows an internal 1.0a current source to pull up the run pin. when the run pin reaches 1.22v, the main control loop is enabled and the ic is powered up. when the run pin is low, all functions are kept in a controlled state. sensing signal of very low dcr the LTC3866 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor dcr, 1m or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. the LTC3866 can sense a dcr value as low as 0.2m with careful pcb layout.the LTC3866 comprises two positive sense pins, snsd + and snsa + , to acquire signals and processes them internally to provide the response as with a dcr sense signal that has a 14db signal-to-noise ratio improvement. in the meantime, the current limit threshold is still a function of the inductor peak current and its dcr value, and can be accurately set from 10mv to 30mv in a 5mv steps with the ilim pin. the filter time constant, r1c1, of the snsd + should match the l/dcr of the output inductor, while the filter at snsa + should have a bandwidth of five times larger than snsd + , r2c2 equals r1c1/5. intv cc / extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5.5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5.5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as a switching regulator output. the top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges dur - ing the off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the dropout transition to ensure c b is recharged. internal soft-start by default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. the internal soft-start ramp connects to the noninverting input of the error amplifier. the fb pin is regulated to the lower of the error amplifiers three noninverting inputs (the internal soft-start ramp, the tk/ss pin or the internal 600mv ref- erence). as the ramp voltage rises from 0v to 0.6v over approximately 600s, the output voltage rises smoothly from its prebiased value to its final set value. certain applications can result in the start-up of the con- verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the bottom mosfet is disabled until soft-start is greater than v fb .
LTC3866 12 3866fb shutdown and start-up (run and tk/ss pins) the LTC3866 can be shut down using the run pin. pulling the run pin below 1.14v shuts down the main control loop for the controller and most internal circuits , including the intv cc regulator. releasing the run pin allows an internal 1.0a current to pull up the pin and enable the controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of the controllers output voltage, v out , is controlled by the voltage on the tk/ss pin, if the internal soft-start has expired. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the LTC3866 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.25a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage, v out , rises smoothly from zero to its final value. alternatively, the tk/ ss pin can be used to cause the start - up of v out to track that of another supply. typically , this requires connect- ing to the tk/ss pin an external resistor divider from the other supply to ground (see the applications information section). when the run pin is pulled low to disable the controller, or when intv cc drops below its undervoltage lockout threshold of 3.75v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, the controller is disabled and the external mosfets are held off . light load current operation (burst mode operation, pulse-skipping or continuous conduction) the LTC3866 can be enabled to enter high efficiency burst mode operation , constant - frequency pulse - skipping mode or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to sgnd. to select pulse-skipping mode of operation, tie the mode/ pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from re- versing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the LTC3866 operates in pwm pulse skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. operation
LTC3866 13 3866fb if the mode/pllin pin is not being driven by an external clock source , the freq pin can be used to program the controllers operating frequency from 250khz to 770khz. there is a precision 10a current flowing out of the freq pin so that the user can program the controllers switch- ing frequency with a single resistor to sgnd. a curve is provided later in the applications information section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is available on the LTC3866 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the pll loop filter network is integrated inside the LTC3866. the phase - locked loop is capable of locking any frequency within the range of 250 khz to 770 khz . the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. the controller operates in forced continuous mode when it is synchronized. sensing the output voltage with a differential amplifier the LTC3866 includes a low offset, high input impedance, unity-gain , high bandwidth differential amplifier for ap- plications that require true remote sensing. sensing the load across the load capacitors directly greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. connect diffp to the output load, and diffn to the load ground. see figure 1. the ltc 3866 differential amplifier has a typical output slew rate of 2v/s. the amplifier is configured for unity gain, meaning that the difference between diffp and diffn is translated to diffout, relative to sgnd. care should be taken to route the diffp and diffn pcb traces parallel to each other all the way to the remote sens- ing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit . ideally, the diffp and diffn traces should be shielded by a low impedance ground plane to maintain signal integrity. power good (pgood pin) the pgood pin is connected to the open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.6v reference voltage. the pgood pin is also pulled low when the run pin is below 1.14v or when the LTC3866 is in the soft-start or tracking up phase. when the v fb pin voltage is within the 10% regulation window, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will flag power good immediately when the v fb pin is within the regulation window . however , there is an internal 20s power-bad mask when the v fb goes out of the window. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. undervoltage lockout the LTC3866 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.75v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 600mv of preci- sion hysteresis. operation figure 1. differential amplifier connection 6 diffout 5 LTC3866 diffp c out v out diffn v fb 3866 f01 ? + diffamp 8 7
LTC3866 14 3866fb operation the typical application on the first page of this data sheet is a basic LTC3866 application circuit . the LTC3866 is designed and optimized for use with a very low dcr value by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14db. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, as the dcr value drops below 1m, the signal-to-noise ratio is low and current sensing is difficult. LTC3866 uses an lt c proprietary technique to solve this issue. in general, external component selection is driven by the load require- ment, and begins with the dcr and inductor value. next, power mosfets are selected. finally, input and output capacitors are selected. current limit programming the ilim pin is a 5-level logic input which sets the maxi- mum current limit of the controller. when ilim is either grounded, floated or tied to intv cc , the typical value for the maximum current sense threshold will be 10mv, 20mv or 30mv, respectively. setting ilim to one-fourth intv cc and three-fourths intv cc for maximum current sense thresholds of 15mv and 25mv. which setting should be used? for the best current limit accuracy, use the highest setting that is applicable to the output requirements. snsd + , snsa + and sns C pins the snsa + and sns C pins are the inputs to the current comparators, while the snsd + pin is the input of an internal amplifier. the operating input voltage range of 0v to 3.5v is for snsa + , sns C and snsd + when the internal differen- tial amplifier is used to remotely sense the output. all the positive sense pins that are connected to the current com- parator or the amplifier are high impedance with input bias currents of less than 1a, but there is also a resistance of about 300 k from the sns C pin to ground . the sns C should be connected directly to v out . the snsd + pin connects to the filter that has a r1c1 time constant matched to l/dcr of the inductor. the snsa + pin is connected to the second filter with the time constant one-fifth that of r1c1. care must be taken not to float these pins during normal operation. filter components, especially capacitors, must be placed close to the LTC3866, and the sense lines should run close together to a kelvin connection underneath the current sense element (figure ?2). because the LTC3866 is designed to be used with a very low dcr value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable . as shown in figure 3, resistors r1 and r2 are placed close to the output inductor and capacitors c1 and c2 are close to the ic pins to prevent noise coupling to the sense signal. figure 2. sense lines placement with inductor dcr c out to sense filter, next to the controller inductor 3866 f02 applications information another way to detect an undervoltage condition is to monitor the v in supply. because the run pin has a preci- sion turn-on reference of 1.22v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current flows out of the run pin once the run pin voltage passes 1.22v. the run comparator itself has about 80mv of hysteresis. one can program additional hysteresis for the run comparator by adjust- ing the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.75v.
LTC3866 15 3866fb applications information the LTC3866 could also be used like any typical current mode controller by disabling the snsd + pin, shorting it to ground. an r sense resistor or a rc filter can be used to sense the output inductor signal and connects to the snsa + pin. if the rc filter is used, its time constant, r ? c, is equaled to l/dcr of the output inductor. in these applications, the current limit, v sense (max) , will be five times larger for the specified ilim, and the operating voltage range of snsa + and sns C is from 0v to 5.25v. without using the internal differential amplifier, the output voltage of 5v can be generated as shown in the typical applications section. inductor dcr sensing the LTC3866 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub milliohm range (figure 3). the dcr is the dc winding resistance of the inductor s copper , which is often less than 1m for high current inductors. in high current and low output voltage applications, a conduction loss of a high dcr or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement, chose the inductor with the dcr that satisfies the maxi- mum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below. dcr = v sense(max) i max + ? i l 2 l/dcr = r1? c1 = 5 ? r2 ? c2 where: v sense(max) : maximum sense voltage for a given ilim threshold i max : maximum load current ?i l : inductor ripple current l, dcr: output inductor characteristics r1, c1: filter time constant of the snsd + pin r2, c2: filter time constant of the snsa + pin to ensure that the load current will be delivered over the full operating temperature range , the temperature coefficient of dcr resistance, approximately 0.4%/c, should be taken into account. the LTC3866 features a dcr temperature compensation circuit that uses an ntc temperature sensing resistor for this purpose. see the inductor dcr sensing temperature compensation section for details. figure 3. inductor dcr current sensing v in v in intv cc boost tg sw bg pgnd itemp r ntc 100k inductor dcrl snsd + snsa + sns ? sgnd LTC3866 v out 3866 f03 r1 c1 c2 place c1, c2 next to ic place r1, r2 next to inductor r1c1 = 5 ? r2c2 r s 22.6k r itemp r p 90.9k r2
LTC3866 16 3866fb applications information typically , c1 and c2 are selected in the range of 0.047f to 0.47f. if c1 and c2 are chosen to be 220nf, and an inductor of 330nh with 0.32m dcr is selected, r1 and r2 will be 4.7k and 942 respectively. the bias current at snsd + and snsa + is about 30na and 500na respectively, and it causes some small error to the sense signal. there will be some power loss in r1 and r2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) C v out ( ) ? v out r ensure that r1 and r2 have a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. to maintain a good signal-to-noise ratio for the current sense signal, using a minimum ?v sense of 2mv for duty cycles less than 40% is desirable. the actual ripple voltage will be determined by the following equation : ? v sense = v out v in ? v in C v out r1c1 ? f osc inductor dcr sensing temperature compensation with ntc thermistor for dcr sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. the main element used in inductors is copper; that has a positive tempco of ap- proximately 4000 ppm / c . the ltc 3866 provides a feature to correct for this variation through the use of the itemp pin. there is a 10a precision current source flowing out of the itemp pin. a thermistor with a ntc (negative tem- perature coefficient) resistance can be used in a network, r itemp (figure 3) connected to maintain the current limit threshold constant over a wide operating temperature. the itemp voltage range that activates the correction is from 0.7v or less. if floating this pin, its voltage will be at intv cc potential, about 5.5v. when the itemp voltage is higher than 0.7 v , the temperature compensation is inactive . the following guideline will help to choose components for temperature correction. the initial compensation is for 25c ambient temperature: itemp ? r itemp = 0.7v for 25c r itemp is a thermistor resistance network connected to itemp pin. since itemp = 10 a, choose r itemp network = 70 k at 25c tc ritemp = C(1.5/0.7) ? tc dcr typically tc dcr = 4000 ppm/c, tempco of dcr which is usually copper. for ideal compensation, the tempco of the r itemp should be: tc ritemp = C(1.5/0.7) ? 4000 ppm/c = C8570 ppm/c for example, a murata ntc thermistor of 100k with b = 4334 that has a nonlinear temperature characteristic as described in r[t] = r[t 0] ? exp b (1/t C 1/ t0) where t0 is the temperature at 300k. resistors r s and r p of 22.6k and 90.9k respectively are used to linearize the network as shown in figure 4.the current limit threshold will be compensated from 25c to over 100c of the inductor temperature , figure 5. once the temperature compensation is done, it will remain valid for all programmable current sense limit scales. inductor temperature (c) 10 resistance (k) 100 1000 10000 ?50 25 50 75 125100 150 1 ?25 0 3866 f04 thermistor resistance r o = 100k t o = 25c b = 4334 for 25c to 100c r itemp r s = 22.6k r p = 90.9k 100k ntc figure 4. resistance versus temperature for the itemp pin network and the 100k ntc
LTC3866 17 3866fb applications information for the most accurate temperature detection, place the thermistor next to the output inductor as shown in figure ?6 . care should be taken to keep the itemp sense line away from switch nodes. pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the LTC3866 can safely power up into a pre-biased output without discharging it. the LTC3866 accomplishes this by disabling both tg and bg until the tk/ss pin voltage and the internal soft-start voltage are above the v fb pin voltage. when v fb is higher than tk/ss or the internal soft-start voltage, the error amp output is railed low. the control loop would like to turn bg on, which would discharge the output. disabling bg and tg prevents the pre-biased output voltage from being discharged. when tk/ss and the internal soft-start both cross 500mv or v fb , whichever is lower, tg and bg are enabled. if the pre-bias is higher than the ov threshold, the bottom gate is turned on immediately to pull the output back into the regulation window. overcurrent fault recovery when the output of the power supply is loaded beyond its preset current limit , the regulated output voltage will collapse depending on the load. the output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. the controller will continue to source current into the short. the amount of current sourced depends on the ilim pin setting and the v fb voltage as shown in the current foldback graph in the typical performance characteristics section. upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. in the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. current limit foldback is not disabled during an overcurrent recovery . the load must step below the folded back current limit threshold in order to restart from a hard short. thermal protection excessive ambient temperatures, loads and inadequate airflow or heat sinking can subject the chip, inductor, fets etc. to high temperatures. this thermal stress re- duces component life and if severe enough, can result in immediate catastrophic failure (note 4). to protect the power supply from undue thermal stress, the LTC3866 has a fixed chip temperature-based thermal shutdown. the internal thermal shutdown is set for approximately 160c with 10c of hysteresis. when the chip reaches 160c, both tg and bg are disabled until the chip cools down below 150c. figure 5. worst-case i max versus inductor temperature curve with and without ntc temperature compensation figure 6. thermistor location. place the thermistor next to the inductor for accurate sensing of the inductor temperature, but keep the itemp pin away from the switch nodes and gate drive traces inductor temperature (c) ?50 i max (a) 15 20 50 25 35 30 45 40 25 75 150 3866 f05 10 5 0 ?25 0 50 100 125 corrected i max uncorrected i max r itemp : r s = 22.6k r p = 90.9k ntc thermistor: r o = 100k t o = 25c b = 4334 nominal i max = 30a v out r ntc l1 sw1 3867 f08
LTC3866 18 3866fb inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in C v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in C v out f osc ? i ripple ? v out v in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase . ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection at least two external power mosfets need to be selected: one n-channel mosfet for the top (main) switch and one or more n - channel mosfet(s) for the bottom (synchro- nous) switch. the number, type and on-resistance of all mosfets selected take into account the voltage step - down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on - resistance with significantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the internal regulator voltage, v intvcc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , input capacitance, input voltage and maximum output current . mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 7). the curve is generated by forcing a constant input current into the gate of a common source , current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to- source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is applications information
LTC3866 19 3866fb due to the drain-to-gate accumulation capacitance and the gate-to- source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in C v out v in ? ? ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? ? f p sync = v in C v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n - channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20 v, the high current efficiency generally improves with larger mosfets , while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short- circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds (on) vs temperature curve , but = 0.005/c can be used as an approximation for low voltage mosfets. an optional schottky diode across the synchronous mosfet conducts during the dead time between the con- duction of the two large power mosfets . this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse - recov - ery period which could cost as much as several percent in efficiency . a 2 a to 8 a schottky is generally a good com- promise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. c in and c out selection in continuous mode , the source current of the top mosfet is a square wave of duty cycle ( v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/2 applications information figure 7. gate charge characteristic + ? v ds v in 3766 f07 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ?
LTC3866 20 3866fb this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief . note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3866, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. ceramic capacitors are becoming very popular for small designs but several cautions should be observed . x 7 r , x 5 r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied . physically , if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input volt- age on a ceramic capacitor, resulting in an audible signal. a secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge . the voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing ! nevertheless , ceramic capacitors , when properly selected and used, can provide the lowest overall loss due to their extremely low esr. a small (0.1f to 1f) bypass capacitor, c in , between the chip v in pin and ground, placed close to the LTC3866, is also suggested. a 2.2 to 10 resistor placed between c in and v in pin provides further isolation. the selection of c out is driven by the required effective series resistance (esr ). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the steady-state output ripple (?v out ) is determined by: ? v out ? i ripple esr + 1 8fc out ? ? ? ? ? ? where f = operating frequency, c out = output capacitance and ?i ripple = ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i ripple increases with input voltage. the output ripple will be less than 50mv at maximum v in with ?i ripple = 0.4 i out(max) assuming: c out required esr < n ? r sense and c out > 1 8f ( ) r sense ( ) the emergence of very low esr capacitors in small , surface mount packages makes very small physical implementa- tions possible. the ability to externally compensate the switching regulator loop using the ith pin allows a much wider selection of output capacitor types. the impedance characteristic of each capacitor type is significantly differ - ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design . manufacturers such as nichicon , nippon chemi - con and sanyo should be considered for high performance through - hole capacitors . the os- con semiconductor dielectric capacitors available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple( p - p ) require- ment. ceramic capacitors from avx , taiyo yuden , murata and tdk offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application . aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv, the kemet t510 series of surface mount tantalums or the panasonic sp series of surface mount special polymer capacitors applications information
LTC3866 21 3866fb applications information available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo poscap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturers for other specific recommendations. differential amplifier the LTC3866 has true remote voltage sense capability. the sense connections should be returned from the load, back to the differential amplifiers inputs through a com- mon, tightly coupled pair of pc traces. the differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback pc traces as well as ground loop disturbances. the LTC3866 diffamp has 80k input impedance on diffp. it is designed to be con- nected directly to the output. the output of the diffamp connects to the v fb pin through a voltage divider, setting the output voltage. external soft-start and tracking the LTC3866 has the ability to either soft-start by itself or track the output of another channel or external supply. when the controller is configured to soft-start by itself, a capacitor may be connected to its tk/ss pin or the internal soft-start may be used. the controller is in the shutdown state if its run pin voltage is below 1.14v and its tk/ss pin is actively pulled to ground in this shutdown state. if the run pin voltage is above 1.22v, the controller powers up. a soft-start current of 1.25a then starts to charge the tk/ss soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp volt- age according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.6v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.25a regardless of the mode selected by the mode/pllin pin, the controller always starts in discontinuous mode up to tk/ss = 0.5v. between tk/ss = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54v. the output ripple is minimized during the 40mv forced continuous mode window, ensuring a clean pgood signal. when the chan- nel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the volt- age ramp rate on this pin is determined by the ramp rate of the other supplys voltage. it is only possible to track another supply that is slower than the internal soft-start ramp. note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the LTC3866 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54v regardless of the setting on the mode/pllin pin. however, the LTC3866 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, the controller operates in discontinuous mode. the LTC3866 allows the user to program how its output ramps up and down by means of the tk/ss pin. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 8. in the following discussions , v out 2 refers to the LTC3866s output as a slave and v out1 refers to another supply output as a master. to implement the coincident tracking in figure 8a, connect an additional resistive di- vider to v out1 and connect its mid-point to the tk/ss pin of the slave controller. the ratio of this divider should be the same as that of the slave controllers feedback divider shown in figure 9a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 8b, the ratio of the v out2 divider should be exactly the same as the master controllers feedback divider shown in figure 9b . by selecting different resis- tors, the LTC3866 can achieve different modes of tracking including the two in figure 8. so which mode should be programmed? while either mode in figure 8 satisfies most practical applications,
LTC3866 22 3866fb time (8a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 3866 f08 (8b) ratiometric tracking output voltage applications information some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. under ratiometric tracking, when the master controllers output experiences dynamic excursion (under load transient, for example), the slave controller output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc (ldo) and extv cc the LTC3866 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the LTC3866s internal circuitry . the ldo regulates the voltage at the intv cc pin to 5.5v when v in is greater than 6v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. either of these can supply a peak current of 100ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to sup- ply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3866 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.5v ldo or extv cc . when the voltage on the extv cc pin is less than 4.5v, the ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics tables . for example , the ltc 3866 intv cc current is limited to less than 39ma from a 38v supply in the uf package and not using the extv cc supply with a 70c ambient temperature: t j = 70c + (39ma)(38v)(37c/w) ? 125c figure 8. tw o different modes of output voltage tracking figure 9. setup and coincident and ratiometric tracking r3 r1 r4 r2 r3 v out2 r4 (9a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3866 f09 (9b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1
LTC3866 23 3866fb applications information to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = sgnd) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the intv cc ldo is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc re- mains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from an efficient switching regulator output during normal operation . if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . significant efficiency and thermal gains can be realized by powering intv cc from extv cc , since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (39ma)(5v)(37c/w) = 77c however, for low voltage outputs, additional circuitry is required to derive intv cc power from the output. the following list summarizes the three possible connec- tions for extv cc : 1. extv cc left open ( or grounded ). this will cause intv cc to be powered from the internal ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected to an external supply. if a 5v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 3. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1 or 2.2 resistor as shown in figure 10 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices. figure 10. setup for a 5v input r vin 1 c in 3866 f10 5v c intvcc 4.7f + intv cc LTC3866 v in topside mosfet driver supply (c b , d b ) external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltages for the topside mos- fet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v db the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet ( s ). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. setting output voltage the LTC3866 output voltage is set by an external feedback resistive divider carefully placed across the diffout pin,
LTC3866 24 3866fb applications information as shown in figure 11. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line. to minimize the effect of the voltage drop caused by high current flowing through board conductance ; connect diffn and diffp sense lines close to the ground and the load output respectively. the resulting short- circuit current is: i sc = 1/3 v sense(max) r sense C 1 2 ? i l sc ( ) ? ? ? ? ? ? after a short, or while starting with internal soft- start, make sure that the load current takes the folded-back current limit into account. phase-locked loop and frequency synchronization the LTC3866 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. there is a precision 10a current flowing out of the freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between the freq pin and the integrated pll filter network is on, allowing the filter network to be pre-charged to the same voltage as the freq pin. the relationship between the voltage on the freq pin and operating frequency is shown in figure 12 and specified in the electrical characteristics table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above turns off and isolates the influence of the freq pin. note that the LTC3866 can only be synchronized to an external clock whose frequency is within range of the LTC3866s internal vco. this is guaranteed to be between 250khz and 770khz. a simplified block diagram is shown in figure 13. figure 11. setting output voltage LTC3866 v fb diffout r b c ff r a 3866 f11 fault conditions: current limit and current foldback the LTC3866 includes current foldback to help limit load current when the output is shorted to ground. if the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maxi- mum value. foldback current limiting is disabled during the soft-start or tracking up using the tk/ss pin. it is not disabled for internal soft-start. under short- circuit condi- tions with very low duty cycles, the LTC3866 will begin cycle skipping in order to limit the short- circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short circuit ripple current is determined by the minimum on- time t on( min) of the LTC3866 (90ns), the input voltage and inductor value: ? i l(sc) = t on(min) ? v in l
LTC3866 25 3866fb applications information if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor c lp holds the voltage. typically , the external clock ( on the mode / pllin pin ) input high threshold is 1.6 v, while the input low threshold is 1v. minimum on- time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC3866 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the voltage ripple and current ripple will increase. the minimum on-time for the LTC3866 is approximately 90ns, with good pcb layout, minimum 30% inductor current ripple and at least 2mv ripple on the current sense signal . the minimum on-time can be affected by pcb switch- ing noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to about 110ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3866 circuits : 1) ic v in current, 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. figure 12. relationship between oscillator frequency and voltage at the freq pin figure 13. phase-locked loop block diagram freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3866 f12 2.5 0 100 300 400 500 900 800 700 200 600 digital phase/ frequency detector vco 2.4v 5.5v 10a r set 3866 f13 freq sync external oscillator mode/pllin
LTC3866 26 3866fb 1. the v in current is the dc supply current given in the electrical characteristics table , which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/ dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets . supplying intv cc power through extv cc from an output - derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(effi- ciency). for example, in a 20v to 5 v application , 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor and current sense re- sistor (if used). in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mos - fet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses . for example , if each r ds(on) = 10 m , r l = 10m, r sense = 5m, then the total resistance is 25m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses, including schottky conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examin- ing the rise time at the pin. the ith external components shown in the typical application circuit will provide an applications information
LTC3866 27 3866fb adequate starting point for most applications . the ith series r c - c c filter sets the dominant pole - zero loop compensation . the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined . the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition . the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance . a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 14. check the following in the pc layout: 1. the intv cc decoupling capacitor should be placed immediately adjacent to the ic between the intv cc pin and pgnd plane. a 1f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets . an additional 4.7f to 10f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. applications information figure 14. branch current waveforms + r in v in v out c in + c out d1 sw2 sw1 l1 dcr r l 3866 f14 bold lines indicate high, switching currents. keep lines to a minimum length
LTC3866 28 3866fb applications information 2. place the feedback divider between the + and C termi- nals of c out . route diffp and diffn with minimum pc trace spacing from the ic to the feedback divider. 3. are the snsd + , snsa + and sns C printed circuit traces routed together with minimum pc trace spacing? the filter capacitors between snsd + , snsa + and sns C should be as close as possible to the pins of the ic. connect the snsd + and snsa + pins to the filter resistors as illustrated in figure 3. 4. do the (+) plates of c in connect to the drain of the topside mosfet as closely as possible? this capacitor provides the pulsed current to the mosfet. 5. keep the switching nodes, sw, boost and tg away from sensitive small-signal nodes (snsd + , snsa + , sns C , diffp, diffn, v fb ). ideally the sw, boost and tg printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv/dt traces from sensitive small - signal nodes with ground traces or ground planes . 6. use a low impedance source such as a logic gate to drive the mode/pllin pin and keep the lead as short as possible. 7. the 47pf to 330pf ceramic capacitor between the i th pin and signal ground should be placed as close as possible to the ic. figure 14 illustrates all branch cur - rents in a switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a com- mon ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfet and schottky diode should return to the bottom plate(s ) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. external opti -loop ? compensa- tion allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure. 8. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter - minals. the v fb and ith traces should be as short as possible. the path formed by the top n-channel mos- fet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 9. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor , the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. design example as a design example of the front page circuit for a single channel high current regulator , assume v in = 12 v ( nominal ), v in = 20 v(maximum), v out = 1.5 v, i max = 30 a, and f = 400khz (see front page schematic). the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? using a 20k 1% resistor from the v fb node to ground, the top feedback resistor is (to the nearest 1% standard value) 30.1k. the frequency is set by biasing the freq pin to 1v (see figure 12). the inductance value is based on a 35% maximum ripple current assumption (10.5a). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1 ? v out v in(max) ? ? ? ? ? ? ? ?
LTC3866 29 3866fb applications information this design will require 0.33h. the wrth 744301033, 0.32h inductor is chosen. at the nominal input voltage (12v), the ripple current will be: ? i l(nom) = v out f ? l 1 ? v out v in(nom) ? ? ? ? ? ? ? ? it will have 10a (33%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 35a. the minimum on-time occurs at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) f = 1.5v 20v(400khz) = 187ns dcr sensing is used in this circuit . if c1 and c2 are chosen to be 220nf, based on the chosen 0.33h inductor with 0.32m dcr, r1 and r2 can be calculated as: r1 = l dcr ? c1 = 4.69k r2 = l dcr ? c2 ? 5 = 937 ? choose r1 = 4.64k and r2 = 931. the maximum dcr of the inductor is 0.34. the v sense(max) is calculated as: v sense(max) = i peak ? dcr max = 12mv the current limit is chosen to be 15mv. if temperature variation is considered, please refer to inductor dcr sensing temperature compensation with ntc thermistor . the power dissipation on the topside mosfet can be easily estimated. choosing an infineon bsc050ne2ls mosfet results in: r ds(on) = 7.1 m ? (max), v miller = 2.8v, c miller ? 35pf. at maximum input voltage with t j (estimated) = 75c: p main = 1.5v 20v 30a ( ) 2 1 + (0.005)(75 c C 25 c) [ ] ? 0.0071 ? ( ) + 20v ( ) 2 30a 2 ? ? ? ? ? ? 2 ? ( ) 35pf ( ) ? 1 5.5v C 2.8v + 1 2.8v ? ? ? ? ? ? 400khz ( ) = 599mw + 122mw = 721mw for a 0.32m dcr, a short- circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 15mv 0.0032 ? C 1 2 90ns(20v) 0.33h ? ? ? ? ? ? = 12.9a an infineon bsc010ne2ls, r ds(on) = 1.1m?, is chosen for the bottom fet. the resulting power loss is: p sync = 20v C 1.5v 20v 30a ( ) 2 ? 1 + 0.005 ( ) ? 75 c C 25 c ( ) ? ? ? ? ? 0.0011 ? p sync = 1.14w c in is chosen for an equivalent rms current rating of at least 13.7a. c out is chosen with an equivalent esr of 4.5m? for low output ripple. the output ripple in continu- ous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.0045? ? 10a = 45mv p-p further reductions in output voltage ripple can be made by placing a 100f ceramic capacitor across c out .
LTC3866 30 3866fb typical applications very low output ripple converter the LTC3866 can work with very low dcr inductors be- cause it can operate with only a small peak-to-peak sense voltage. tw o inductor characteristics can diminish this signal: lower dc resistance and higher inductance. while lower dcr improves efficiency, higher inductance reduces output ripple. because the LTC3866 only requires a ripple signal about a quarter of the sense signal of the next best current mode converters, output ripple can be drastically reduced by increasing the inductance and capacitance of the output filter. the very small output voltage ripple is critical for low noise applications such as audio systems and noise sensitive systems. the schematic as shown figure 15 is similar to that of the front page circuit , except that three times the inductance and double the output capacitance are used. the com- pensation components are changed to maintain the same crossover frequency and phase margin. figure 16 shows the transient response of 15a load step, and figure 17 demonstrates that the output voltage ripple is a factor of six smaller than that of typical current mode converters. increasing the inductance, while maintaining the same physical size inductor, will invariably increase conduction losses due to higher dc resistance . however , reduced ripple current will decrease the core loss and the ac resistance loss often enough to negate the extra dc conduction losses. figure 18 shows a high efficiency converter with the benefit of low output ripple current. freq mode/pllin run pgood tk/ss itemp ith extv cc v fb v in diffout intv cc diffp boost diffn tg snsd + sw sns ? bg c out 470f 4 0.1f r2 909 r1 4.53k 3866 f15 r b 30.1k 100k 0.1f r a 20k 10k v out 1.5v 25a 4.7f c1 220nf c2 220nf 680pf 75pf bsc050ne2ls bsc010ne2ls cmdsh-3 220f v in 4.5v to 20v l1 1h dcr = 1m snsa + pgnd ilim clkout LTC3866 sgnd figure 15. high efficiency, 1.5v/25a step-down converter with very low output ripple
LTC3866 31 3866fb typical applications i l 10a/div 0a v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.5v 3866 f16 figure 16. load step transient response figure 17. very low output voltage ripple figure 18. power efficiency vs load current 5v/25a step-down converter v out low ripple figure 15 10mv/div ac-coupled v out typical front page 10mv/div ac-coupled 2s/div 3866 f17 v in = 12v v out = 1.5v load current (a) 0.01 0 efficiency (%) 10 30 40 50 100 70 0.1 1 3866 f18 20 80 90 60 10 100 v in = 12v v out = 1.5v freq mode/pllin run pgood tk/ss itemp ith extv cc v fb v in diffout intv cc diffp boost diffn tg snsd + sw sns ? bg 100f 2 330f 2 v out r1 3.48k 3866 ta04 r2 147k 20k 28.7k r3 20k v out 5v 25a 4.7f cmdsh-3 bsc024ne2ls bsc010ne2ls 1f 120k 2.2 c1 220nf v in 12v l1 1h dcr = 1.3m snsa + pgnd ilim clkout LTC3866 sgnd 10f 2 180f 2 2.2nf 100pf 0.1f
LTC3866 32 3866fb typical applications 100f 2 freq mode/pllin run 100k 0.1f 330pf 3.57k 20k 30.1k pgood tk/ss itemp ith extv cc v in v fb diffout intv cc diffp boost tg diffn snsd + sns ? snsa + pgnd bg sw i lim clkout LTC3866 sgnd 30.1k 120k 2.2 v in 7v to 20v 931 4.64k v out 1.5v 60a 0.33h dcr = 0.32m 0.33h dcr = 0.32m gnd 10k 202nf 220nf 0.1f bsc050ne2ls bsc010ne2ls cmdsh-3 10f 2 330f 2 4.7f 220nf 1f 100f 2 freq mode/pllin run 100k pgood tk/ss itemp ith extv cc v in v fb diffout intv cc diffp boost tg diffn snsd + sns ? snsa + pgnd bg sw i lim clkout LTC3866 sgnd 120k 931 4.64k 3866 ta02 220nf 0.1f bsc050ne2ls bsc010ne2ls cmdsh-3 10f 2 330f 2 4.7f 220nf 1f high efficiency, dual phase very low dcr sensing 1.5v/60a step-down supply
LTC3866 33 3866fb fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa fe24 (aa) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
LTC3866 34 3866fb uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
LTC3866 35 3866fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 08/12 clarified operating temperatures. modified the p d equation thermal resistance value. modified the block diagram sense amplifier. clarified the sns section values. modified the ripple value in the soft-start section. modified values in the intv cc and extv cc section. modified the 5v/25a step-down converter circuit schematic. 2-5 5 10 14 21 22-23 31 b 10/12 added "junction to clarify operating temperature range. 3, 4, 5
LTC3866 36 3866fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1012 rev b ? printed in usa related parts typical application part number description comments ltc3833 fast accurate step-down dc/dc controller with differential output sensing very fast transient response, t on(min) = 20ns, 4.5v v in 38v, 0.6v v out 5.5v, tssop-20e, 3mm 4mm qfn-20 ltc3878/ltc3879 no r sense ? constant on- time synchronous step-down dc/dc controllers very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v v out 0.9v in , ssop-16, msop -16e, 3mm 3mm qfn-16 ltc3775 high frequency synchronous voltage mode step-down dc/dc controller very fast transient response, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v in , msop-16e, 3mm 3mm qfn-16 ltc3854 small footprint synchronous step-down dc/dc controller fixed 400khz operating frequency, 4.5v v in 38v, 0.8v v out 5.25v, 2mm 3mm qfn-12 ltc3851a/ltc3851a-1 no r sense wide v in range synchronous step-down dc/dc controllers pll fixed frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3891 60v, low i q synchronous step-down dc/dc controller pll capable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3856 2-phase, single output synchronous step- down dc/dc controller with diff amp and dcr temp compensation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.6v v out 5.25v ltc3829 3-phase, single output synchronous step-down dc/dc controller with diff amp and dcr temp compensation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.6v v out 5.25v ltc3855 2-phase, dual output synchronous step-down dc/dc controller with differential remote sense pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.6v v out 12.5v ltc3860 dual, multiphase, synchronous step-down dc/dc controller with diff amp and three-state output drive operates with power blocks, drmos devices or external drivers/ mosfets , 3v v in 24v, t on(min) = 20ns ltc3869/ltc3869-2 2-phase, dual output synchronous step-down dc/dc controllers, with accurate multiphase current matching pll fixed frequency 250khz to 780khz, 4v v in 30v, 0.6v v out 12.5v, 4mm 5mm qfn-28, ssop-28 ltc3867 synchronous step-down dc/dc controller with nonlinear control and remote sense fast transient response, t on(min) = 65ns, 4v v in 38v, 0.6v v out 14v, 4mm 4mm qfn-24 high efficiency step-down converter with power block cmdsh-3 100k 1f 100k 10k 20k 30.1k 4.75k intv cc 0.1f 0.1f 1500pf 220pf 47nf 47nf 25 7 8 9 10 11 24 23 22 21 20 19 intv cc 4.7f v in v in v out intv cc 2.2 acbel power block vra001-4c1g 18 17 16 15 14 13 1 2 3 4 5 6 12 ith v fb diffout diffn diffp snsd + extv cc v in intv cc boost tg sw bg v in1 v in2 pwmh pwml v gate gnd gnd gnd gnd v out1 v out2 1 7 5 4 3 2 6 9 13 11 12 15 14 10 8 temp + temp ? cs ? cs + tk/ss run freq mode/pllin pgood itemp sns? snsa+ ilim clkout pgnd sgnd LTC3866euf 100f 330f 330f 470f 10f + + v out 1.5v 40a gnd 3866 ta03 10 10

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